FIG. 11 is a diagram showing the configuration of a conventional semiconductor memory device including an ECC (error checking and correction) codec (coder/decoder circuit). FIG. 11 is based on FIG. 1 of Patent Publication 1 and forms the premises of the present invention, and hence is now described schematically.
Referring to FIG. 11, this semiconductor memory device is a clock synchronized type SDRAM (synchronous dynamic random access memory) including four memory cell arrays 11A to 11D in association with four memory banks. Each of the memory cell arrays 11A to 11D includes a matrix array of dynamic memory cells. The gate terminal of a memory cell transistor, not shown, is connected to a word line, not shown. One of the drain and the source of the memory cell transistor is connected to complementary bit lines, not shown, from row to row, and the other of the drain and the source of the memory cell transistor is connected to one end of a capacitor for data storage. A word driver, not shown, drives the selected word line, not shown, of the memory cell array to a boosted potential, in accordance with the decoded result of the row address by the row decoders 3A to 3D. The complementary bit lines, not shown, of the memory cell array, are connected to the I/O line by sense amplifiers 12A to 12D and column decoders 2A to 2D. The sense amplifier receives and amplifies the potential difference developed across the complementary bit lines by data read from the memory cell. The I/O bus (IO BUS) is commonly used by the respective memory banks and connected to an output terminal of an input circuit 4 and to an input terminal of an output circuit 5 via a multiplexer 6. A terminal DQ is a data input/output terminal.
An address signal, supplied from an address input terminal AD, is entered to and held by a row column address buffer 8. An X(row)-address is supplied to row address decoders 3A to 3D, while a Y(column)-address is supplied to column decoders 2A to 2D.
A refresh counter 9 generates a row address for self-refresh. During the self-refresh, the row address from the refresh counter 9 is selected in place of the external address AD and supplied to the row decoders 3A to 3D. The data of the memory cells, connected to a selected word line corresponding to the row address, are read on the respective bit lines and amplified by the sense amplifiers so as to be re-stored in the memory cells.
A self-refresh circuit 22 controls the operation and the period of self-refresh.
A command decoder 21 receives and decodes external and internal commands, depending on the operating mode. More specifically, the command decoder 21 is supplied with a clock signal CLK, a clock enable signal CKE, a chip enable signal /CE, a column address strobe signal /CAS, a row address strobe signal /RAS and a write enable signal /WE to generate internal timing signals for controlling the operating mode of the SDRAM and the operation of the respective circuit blocks, based on the signal level changes or timings. The chip enable signal /CE at its low level commands a start of a command input cycle. When the chip enable signal /CE is at a high level (or a chip non-selection state), other inputs are not significant. However, a memory bank selection state and an internal operation such as a burst operation are not influenced by a change to the chip non-selection state. Functions of the respective signals such as the /RAS, /CAS, and /WE are different from those of the corresponding signals in a ordinary DRAM, and these signals are made to be significant when a command cycle is defined.
The clock enable signal CKE is the signal to instruct effectiveness of the subsequent clock signal CLK. The clock enable signal CKE at a high level indicates that the rising edge of the subsequent clock signal CLK is effective. The clock enable signal CKE at a low level indicates that the rising edge of the subsequent clock signal CLK is ineffective.
In the configuration shown in FIG. 11, the command decoder 21 includes an ECC mode decoder 31 and a self mode decoder 32, in addition to the function of a command decoder for ordinary commands, such as bank-active, read/write or pre-charge. The command decoder 21 generates a row-address strobe signal φ RAS, based on a self-refresh signal φ SRF, supplied from the self-refresh circuit 22, to send the so generated signal to the row column address buffer 8.
When the clock enable signal CKE has changed from a high level to a low level, the ECC mode decoder 31 decodes the chip enable signal /CE, row address strobe signal /RAS, column address strobe signal /CAS and write enable signal /WE, all of which are supplied in synchronism with the clock signal CLK. When it is judged that the setting is that for a data retention operating mode, realizing super low power consumption, with the internal power supply circuit being partially turned off, the ECC mode decoder 31 generates a high-level encoding start signal ENST to send the so generated signal to an ECC controller 23, while setting a super low power flag SLPF (Super Low Power Flag), and an encoding flag, not shown, indicating that an ECC circuit (ECC codec) 24 is in the encoding state (in the state of generating the parity by the encoding circuit), to an activated state. On receipt from the ECC controller 23 of an encoding end signal ENED, indicating that the encoding in the ECC circuit 24 has come to a close, the ECC mode decoder 31 resets the encoding flag.
When a command for canceling the data retention mode has been supplied from outside, by the clock enable signal CKE changing from a high level to a low level, the ECC mode decoder 31 resets the super low power flag SLPF. At this time, the ECC mode decoder 31 judges, based on the set state or the reset state of the encoding flag, whether the state which has prevailed so far is                such a state where, with the current mode being a data retention mode, the ECC circuit 24 has finished the encoding, or        such a state where, with the current mode being a ordinary self-refresh mode, the ECC circuit 24 is not engaged in the encoding operation. If, as a result of the above judgement, the operating mode is the data retention mode, and the ECC circuit 24 has finished the encoding, the ECC mode decoder 31 generates a decoding start signal DEST of an activated state (high level) to send the so generated signal to the ECC controller 23, while setting a decode flag, not shown, indicating that the decoding by the ECC circuit 24 (the operation of correcting errors by the decoding circuit) is under way. When supplied from the ECC controller 23 with a decoding end signal DEED indicating that the decoding in the ECC circuit 24 has come to a close, the ECC mode decoder 31 resets the decode flag.        
If, when the potential at a preset internal location, supplied from an internal power supply circuit 27 has reached a preset value, and the internal power supply ON signal GON, indicating that the internal power supply has been turned on, has been changed from an inactivated state (low level) to an activated state (high level), the super low power flag SLPF is set, the ECC mode decoder 31 sets a second self-refresh start signal SRT2 to an activated state (high level). If, when the internal power supply ON signal GON has been changed from the inactivated state (low level) to the activated state (high level), the super low power flag SLPF has been reset, the second self-refresh start signal SRT2 is set to an activated state (high level). The ECC mode decoder 31 generates a decode start signal DEST in the activated state (high level), and sends the so generated signal to the ECC controller 23, while setting the decode flag.
If, when the clock enable signal CKE has changed from a high level to a low level, the self mode decoder 32 decodes the chip enable signal /CE, row address strobe signal /RAS, column address strobe signal/CAS and the write enable signal /WE, supplied in synchronism with the clock signal CLK, and has verified that the current operating mode is not the data retention mode but is a ordinary self-refresh mode, the self mode decoder generates a first self-refresh start signal SRT1 in the activated state (high level) to send the so generated signal to the self-refresh circuit 22 and to an OR circuit 28.
If, when the clock enable signal CKE has been changed from a high level to a low level, the self mode decoder 32 decodes the chip enable signal /CE, row address strobe signal /RAS, column address strobe signal/CAS and the write enable signal /WE, supplied in synchronism with the clock signal CLK, and has judged that the current mode is the data retention mode, the self mode decoder sets the super low power flag as the internal state flag, not shown. Meanwhile, it is sufficient that the super low power flag for the ECC mode decoder 31 is set to the same value as that for the self mode decoder 32 and hence the super low power flag for the ECC mode decoder 31 or that for the self mode decoder 32 may be used as a value of the signal line SLPF of FIG. 11.
If, when the command for canceling the data retention mode is supplied from outside, by the clock enable signal CKE changing from a high level to a low level, the self mode decoder 32 resets the super low power flag, not shown, while also resetting the first self-refresh start signal SRT1 and the second self-refresh start signal SRT2, also termed ‘burst refresh signals’, to the non-activated state (low level).
When supplied from the ECC controller 23 with the encoding end signal ENED, the self mode decoder 32 generates the second self-refresh start signal SRT2 in the activated state, and sends the so generated signal to the self-refresh circuit 22, OR circuit 28 and to the ECC mode decoder 31, in case the super low power flag SLPF has been set. In a similar manner, if, when the internal power supply ON signal GON, supplied from the internal power supply circuit 27, is changed from the inactivated state (low level) to the activated state, the super low power flag is set, the self mode decoder 32 generates the second self-refresh start signal SRT2 in the activated state, and sends the so supplied signal to the self-refresh circuit 22, OR circuit 28 and to the ECC mode decoder 31.
When supplied with the decoding end signal DEED in the activated state (high level), the self mode decoder 32 generates the first self-refresh start signal SRT1 in the activated state (high level), and sends the so generated signal to the self-refresh circuit 22 and to the OR circuit 28.
The self-refresh circuit 22 changes the oscillation frequency of a clock signal, generated by an internally provided oscillator, not shown, based on the first self-refresh start signal SRT1 or the second self-refresh start signal SRT2, in the activated state (high level), supplied from the self mode decoder 32, to generate the self-refresh signal φ SRF, which is sent to the command decoder 21.
When supplied with the first self-refresh start signal SRT1 in the activated state (high level), the self-refresh circuit 22 sets the oscillation frequency of the clock signal, generated by an oscillator, not shown, so that the refresh period TR will be a preset period. When supplied with the second self-refresh start signal SRT2 in the activated state (high level), the self-refresh circuit 22 sets the oscillation frequency of the clock signal, generated by the oscillator, not shown, so that the refresh period TR will be shorter than the usual refresh period, for effecting burst self-refresh.
If, as a result of termination of the burst self-refresh for the entire word lines of the entire memory cell arrays 11A to 11D, the value of an internally provided counter has become equal to a preset value corresponding to the number of the word lines, the self-refresh circuit 22 generates a self-refresh end signal SRED in the activated state (high level), indicating the end of the burst self-refresh, and sends the so generated signal to the self mode decoder 32 and to the timer 26.
Based on the self-refresh end signal SRED, the self-refresh circuit 22 generates an internal power supply OFF signal GOFF in the activated state, commanding the OFF of the internal power supply circuit 27, and sends the resulting signal to the internal power supply circuit 27.
Based on an internal power supply OFF end signal PEND, supplied from the timer 26, and which is indicative of the lapse of the time for turning off the internal power supply circuit 27 (also termed herein the ‘internal power supply OFF time’), the self-refresh circuit 22 changes the internal power supply OFF signal GOFF from the activated state (high level) to the non-activated state (low level) and sends the resulting signal to the internal power supply circuit 27.
Based on the encoding start signal ENST, in the activated state (high level), supplied from the ECC mode decoder 31, the ECC controller 23 generates an internal command, an address signal AD and an encoding flag ENC for controlling the read/write operation during encoding, in synchronism with the internal clock signal CLKIn supplied from an internal clock circuit 25, and sends the internal command and the address signal AD to the command decoder 21, while sending the encoding flag ENC to the ECC circuit 24.
The command decoder 21 captures the internal command by a rising edge of the internal clock signal CLKIn as the signal changes from low to high.
When the parity calculations and the operation of writing of the parity field into all memory cells making up the memory cell arrays 11A to 11D, in the ECC circuit 24, the ECC controller 23 sends the encoding end signal ENED to the ECC mode decoder 31.
Based on the decoding start signal DEST, in the activated state (high level), supplied from the ECC mode decoder 31, the ECC controller 23 generates an internal command, an address signal AD and a decode flag DEC for controlling the readout/write during decoding, in synchronism with the internal clock signal CLKIn, and sends the internal command and the address signal AD to the command decoder 21, while sending the encoding flag ENC to the ECC circuit 24.
When the decoding as commanded has been finished in the ECC circuit 24, the ECC controller 23 sends the decoding end signal DEED to the ECC mode decoder 31 and to the self mode decoder 32.
Based on the encoding flag ENC, supplied from the ECC controller 23, the ECC circuit 24 accesses the memory cell arrays 11A to 11D, via multiplexer (MUX) 6, in synchronism with the internal clock signal CLKIn, supplied from the internal clock circuit 25, to perform parity calculations for correcting the errors of refresh failure bits and writing in the parity field in the memory cells.
In addition, based on the decode flag DEC, supplied from the ECC controller 23, the ECC circuit 24 accesses the memory cell arrays 11A to 11D, via multiplexer (MUX) 6, in synchronism with the internal clock signal CLKIn, to perform parity bit calculations and error correction of refresh failure bits.
The internal clock circuit 25 generates the internal clock signal CLKIn, employed by the ECC controller 23 and the ECC circuit 24.
Based on the self-refresh end signal SRED of a high level, supplied from the self-refresh circuit 22, the timer 26 commences the time count of the preset internal power supply OFF time, programmed using e.g. fuses. After lapse of the internal power supply OFF time, the timer 26 sends an internal power supply OFF end signal PEND to the self-refresh circuit 22.
If the super low power flag SLPF is reset during time count of the internal power supply OFF time, by the clock enable signal CKE going high from low, the timer 26 discontinues the time count of the internal power supply OFF time, and sends the internal power supply OFF end signal PEND of the high-level to the self-refresh circuit 22.
The internal power supply circuit 27 sends, to various parts of the semiconductor memory device, a variety of internal voltages, such as word line boost voltage (VPP), bit line potential, one-half of the bit line potential, plate voltage (VPLT), potential of the peripheral or the memory cell part substrate potential (VBB), while sending a high level activation signal ACT for supplying the above internal voltage or the external voltage to column decoders making up a set of column decoders 2A to 2D, row decoders making up a set of row decoders 3A to 3D, or to peripherals, such as a random logic.
Based on the internal power supply OFF signal GOFF of a high level, in the activated state, supplied from the self-refresh circuit 22, the internal power supply circuit 27 also halts the supply of the internal voltage to various parts of the semiconductor memory device, while causing the activation signal ACT to be changed from the activated (high level) state to the inactivated (low level) state to send the resulting signal to the peripheral circuitry. Moreover, when the internal power supply OFF signal GOFF, supplied from the self-refresh circuit 22, is changed from the activated state (high level) to the inactivated state (low level), the internal power supply circuit 27 commences to supply the internal voltage to various parts of the semiconductor memory device and causes the activation signal ACT to be changed from the inactivated (low level) state to the activated (high level) state to send the resulting signal to the peripheral circuitry. The internal power supply circuit 27 also monitors one of the potentials applied to various parts that takes the longest time until reaching a preset potential value, such as VPP or VBB, and detects that the potential in question has reached the preset potential value to send the internal power supply ON signal GON in the activated (high level) state to the ECC mode decoder 31 and to the self mode decoder 32.
The OR circuit 28 takes the logical sum of the first and second self-refresh start signals SRT1 and SRT2 to send the result to the row column address buffer 8.
FIG. 12 is a diagram showing an example of status transition of the semiconductor memory device shown in FIG. 11 hereof (see also FIG. 4 of Patent Publication 1).
When a command for entry to the data retention mode (SPC) is entered, a DRAM device, which has an ECC circuit on-chip and which performs power control during standby time to realize the data retention mode of low power consumption, enters from the normal operating mode (idle state IST) into the data retention mode. In the idle state (IST), the DRAM device waits for an access request (command) from a DRAM controller, not shown, and executes the access request when the access request is actually issued.
The ECC circuit 24 encodes the entire bits of the memory cell array to cause check bits (parity) to be stored in a check bit area in the memory cell array, that is, the ECC is in an encoding state (EEST). With the ECC encoding state (EEST), calculation of parity bits and writing the parity bits into the parity area of the memory cell array for correcting error of refresh failure bit are carried out by the ECC circuit 24 formed in the semiconductor chip.
When the encoding by the ECC circuit 24 is finished, and the encoding end signal ENED is received from the ECC controller 23, the self mode decoder 32 generates the second self-refresh start signal SRT2 to change from the ECC encoding state to the burst self-refresh state BSST. In contradistinction from the ordinary self-refresh, in which the refresh is carried out in a distributed fashion with the refresh period TR as set in dependence upon the refresh tolerance tREF, the refresh in the burst self-refresh state BSST is carried out in a burst with a shorter refresh period TR.
When the burst self-refresh for the entire word lines of the memory cell arrays 11A to 11D is finished, the self-refresh circuit 22 outputs a self-refresh end signal SRED to the self mode decoder 32 and to the timer 26. The self-refresh circuit 22 also generates the internal power supply OFF signal GOFF to send the so generated signal to the internal power supply circuit 27. The state then is changed from the self-refresh state to a power-off state PFST. In this power-off state PFST, part of the internal power supply voltage ceases to be supplied to the inside of the semiconductor memory device.
When the internal power supply OFF time has elapsed, the timer 26 outputs an internal power supply OFF end signal PEND to the self-refresh circuit 22. Based on the internal power supply OFF end signal PEND, the self-refresh circuit 22 inactivates the internal power supply OFF signal GOFF, used for activating the internal power supply circuit 27. The transition is made from the power-off state PFST to a power On state PNST.
When it is detected that the power supply potential, monitored by the internal power supply circuit 27, has reached a preset potential, the high-level internal power supply OFF signal GOFF is supplied to the ECC mode decoder 31 and to the self mode decoder 32. Since the internal power supply OFF signal GOFF is at a high level, with the operating mode being the data retention mode, the ECC mode decoder 31 generates the second self-refresh start signal SRT2 to move from the power On state PNST to the burst self-refresh state BSST.
If, with the burst self-refresh state BSST, the clock enable signal CKE is changed from a low level to a high level to render the rise of the clock signal CLK valid, and a preset exit command is entered, in order to cancel the super low power consumption mode (data retention mode), the ECC mode decoder 31 resets the super low power flag SLPF. The self mode decoder 32 also resets the super low power flag (internal), as the internal state flag, to cause the second self-refresh start signal SRT2 to change from high to low. The ECC mode decoder 31 generates a high-level decoding start signal DEST to send the signal to the ECC controller 23. This causes transition from the burst self-refresh state to the ECC decoding state EDST.
When the decoding in the ECC circuit 24 has been finished and the high-level decoding end signal DEED is received from the ECC mode decoder 31, the self mode decoder 32 generates the first self-refresh start signal SRT1 to make transition from the ECC decoding state EDST to the self-refresh state SRST.
For canceling the self-refresh state SRST, the clock enable signal CKE is caused to go from low to high. The self mode decoder 32 causes the first self-refresh start signal SRT1 to go from high to low. The self-refresh circuit 22 discontinues to generate the self-refresh signal φ REF, based on the low-level first self-refresh start signal SRT1. The command decoder 21 discontinues to generate the row-address strobe signal φ RAS because it is not supplied with the self-refresh signal φ REF from the self-refresh circuit 22, and transition is made from the self-refresh state SRST to the idle state IST.
In the ECC encoding state and in the ECC decoding state, there are occasions where the refresh operations are inserted from time to time in view of much time taken depending on the volume of the error detection/correction operations.
In this manner, the on-chip ECC circuit is provided to exercise power control, the refresh period is extended and refresh fail cells are restored by error correction by the ECC circuit, thereby enabling the long-term refresh with a refresh period equal to or longer than 1 sec, as well as reduction of the data retention current (reduction of the power supply current) (see Patent Publication 2). The super low power consumption data retention operation mode, realizing the long-term refresh with the refresh period exceeding the device tolerance (real power of the data retention characteristics) by the error correction with the ECC circuit, is herein termed the super self refresh mode (SSR mode).
[Patent Publication 1]
JP Patent Kokai Publication JP-P2003-68076A
[Patent Publication 2]
JP Patent Kokai Publication JP-P2002-56671A